학술논문
The application of Transmission Line Pulse testing for the ESD analysis of integrated circuits
Document Type
Conference
Author
Source
2001 Electrical Overstress/Electrostatic Discharge Symposium Electrical Overstress/Electrostatic Discharge Symposium, 2001. EOS/ESD '01.. :421-429 Sep, 2001
Subject
Language
Abstract
TLP, well known for device characterisation, applied to full integrated circuits offers valuable data for analysis of ESD behaviour. TLP is the only method to study ESD behaviour during zapping and as such provides knowledge about actual ESD current paths. As illustrated by examples, this gives valuable suggestions for improving circuit designs.