부산대학교 도서관

Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO 3 thin dielectrics with a monolayer CVD MoS 2 , where the optimized SrTiO 3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10 -2 A/cm 2 ). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to ~75 mV dec -1 and a large ON/OFF current ratio of 10 6 .