부산대학교 도서관

This paper proposes a mm-wave all-digital PLL (ADPLL) employing a 4× reference oversampling (ROS) phase detector (PD). The fractional-N operation is assisted by two capacitive DACs embedded in the ROS-PD. Exploiting the benefits of all-digital implementation, differential/offset mismatches can be compensated by CDAC and zeroed out through a 4-tap moving average (MA) to reduce the reference spurs. The proposed fractional-N ADPLL is implemented in 28 nm CMOS. It achieves rms jitter of 237 fs at a carrier of 28.8 GHz when using a standard 50 MHz crystal oscillator, while consuming only 11.9 mW, leading to FoM jitter−N of -269.3 dB.