부산대학교 도서관

This paper proposes a hybrid time-voltage phase digitization technique in an all-digital phase-locked loop (ADPLL). To cover the required dynamic range of one oscillator period to measure the phase difference between clock edges of reference and feedback from a high-frequency oscillator, a digital-to-time converter (DTC) is used to reduce the required range of a time-to-digital converter (TDC). Further, a time error is first converted to voltage through a time-to-voltage converter (TVC) and further quantized to digital bits by a SAR-ADC. This results in a high-resolution phase detection which can help reducing the in-band phase noise while consuming low power. The system has been modeled and verified based on an event-driven approach in 28 nm CMOS.