부산대학교 도서관

In this paper, we propose an innovative methodology for building a Spiking Neural Network (SNN) by using compact Field Programmable Gate Arrays (FPGA) and an analog chip, which addresses the widespread need for efficient and scalable neural network solutions. Specifically, we partition the neural network into two components: The FPGA hosts the neural network itself, while the analog chip houses the spike response function. These elements are seamlessly integrated into a unified System on a Chip (SoC). The analog chip is engineered using passive component circuits, including RC and RLC circuits, which furnish the decay behavior crucial for existing spiking models. Our approach confers several advantages, including heightened efficiency and scalability, as comprehensive simulations demonstrate. Our findings underscore the efficacy of image recognition, attaining elevated accuracy while substantially reducing the requisite hardware resources. This methodology is intended for application in smart cameras for pervasive surveillance, leveraging the cost-effectiveness and low power consumption of the SoC.