학술논문
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode
Document Type
Conference
Author
Source
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International. :459-466 2006
Subject
Language
ISSN
0193-6530
2376-8606
2376-8606
Abstract
A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm 2 die with an effective cell-size of 0.7191mum 2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst