학술논문

Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last
Document Type
Conference
Source
2023 IEEE International 3D Systems Integration Conference (3DIC) 3D Systems Integration Conference (3DIC), 2023 IEEE International. :1-4 May, 2023
Subject
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Power, Energy and Industry Applications
Radio frequency
Rapid prototyping
Silicon
Filling
Through-silicon vias
Standards
Three-dimensional integrated circuits
3D-IC. TSV
Via-last
PVD
Die-to-Wafer
Language
ISSN
2836-4902
Abstract
The increasing demands for high-quality and high-aspect-ratio Through-Silicon Vias (TSVs) in three-dimensional integrated circuits (3D-IC) have made Si process technologies a significant challenge. Long-throw ionized Physical Vapor Deposition (iPVD) is widely used for barrier/seed layer deposition prior to Cu filling by electroplating for TSV. However, a micro-scale shadowing effect in deep Si holes with high aspect ratios results in failed filling. Bosch etching process can form the high-aspect-ratio deep Si holes but it leaves nuisance scallop features that further increase another submicron-scale shadowing effect. This study aims to explore the impact of super long-throw iPVD with low-frequency RF substrate bias to form high-aspect-ratio TSVs and compares the Cu coverages with a standard magnetron sputtering of non-ionized PVD for 3D-IC rapid prototyping.