학술논문
Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space
Document Type
Conference
Author
Mertens, H.; Ritzenthaler, R.; Oniki, Y.; Briggs, B.; Chan, B.T.; Hikavyy, A.; Hopf, T.; Mannaert, G.; Tao, Z.; Sebaai, F.; Peter, A.; Vandersmissen, K.; Dupuy, E.; Rosseel, E.; Batuk, D.; Geypen, J.; Martinez, G. T.; Abigail, D.; Grieten, E.; Dehave, K.; Mitard, J.; Subramanian, S.; Ragnarsson, L.-A.; Weckx, P.; Jang, D.; Chehab, B.; Hellings, G.; Ryckaert, J.; Litta, E. Dentoni; Horiguchi, N.
Source
2021 Symposium on VLSI Technology VLSI Technology, 2021 Symposium on. :1-2 Jun, 2021
Subject
Language
ISSN
2158-9682
Abstract
We report on forksheet N- and PFETs co-integrated with gate-all-around nanosheet FETs. The forksheet short-channel control is on par with nanosheets down to 22nm gate length (SS SAT =66-68mV/dec). Forksheet I ON and I OFF characteristics are improved by post-channel-release wet clean optimization, attributed to gate stack interface trap density reduction. Dual work function metal gates are integrated at 17nm N-P space, highlighting a key benefit of forksheets for CMOS area scaling.