학술논문

Optimization of Vertical GaN Drift Region Layers for Avalanche and Punch-Through Pn-Diodes
Document Type
Periodical
Source
IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 44(3):388-391 Mar, 2023
Subject
Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
Doping
Resistance
Gallium nitride
Temperature measurement
Substrates
Electric breakdown
Electrical resistance measurement
Gallium Nitride
GaN
vertical
pn-Diode
diode
drift Layer
avalanche
punch-through
Language
ISSN
0741-3106
1558-0563
Abstract
We optimized gallium nitride drift layers for high voltage and low resistance vertical electronic devices by tuning the doping concentration for a given thickness of $5~\mu \text{m}$ . The optimization procedure is based on an empirical mobility model in order to maximize the corresponding device’s power figure-of-merit with respect to the drift layers parameters. We demonstrate quasi-vertical gallium-nitride based avalanche and punch-through pn-diodes grown on sapphire substrates and we compare the results to the theoretical breakdown voltage values as a function of the drift region doping concentration and thickness. We report on a pn-diode with 545 V avalanche breakdown voltage and a specific resistance of 0.34 $\text{m}\Omega $ cm2 resulting in a power figure-of-merit of 874 MW / cm2 and a punch-through pn-diode with 920 V breakdown voltage, specific resistance of 0.57 $\text{m}\Omega $ cm2 resulting in a power figure-of-merit of 1.48 GW / cm2.