학술논문
A fully planarized 8M bit ferroelectric RAM with 'chain' cell structure
Document Type
Conference
Author
Source
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) VLSI technology VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on. :113-114 2001
Subject
Language
Abstract
A 8M-bit fully functional ferroelectric RAM (FeRAM) with 0.25 /spl mu/m CMOS process was successfully fabricated by using a highly reliable Pt-SRO-PZT-SRO-Pt stacked capacitor and aluminum reflow based low damage metallization process. The chip area of 76 mm/sup 2/ was achieved by using a 'chain' cell structure.