학술논문
NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector
Document Type
Periodical
Author
Source
IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 44(4):614-617 Apr, 2023
Subject
Language
ISSN
0741-3106
1558-0563
1558-0563
Abstract
NPN latch-up memory selector devices featuring SiGe hetero-junctions are fabricated and measured electrically. 25% Ge is introduced into the floating base layer by epitaxy. The performance of this device is compared against an implanted Si stack. It is observed that the addition of 25% Ge in the floating base layer of these latch-up selector devices boosts the non-linearity by more than $\times {100}$ and enables abrupt latch-up below 2V. TCAD simulations comparing drift-diffusion and hydro-dynamic models are used to validate our understanding of the device.