학술논문
A CMOS ADSL codec for central office applications
Document Type
Periodical
Author
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 36(3):356-365 Mar, 2001
Subject
Language
ISSN
0018-9200
1558-173X
1558-173X
Abstract
A CMOS central office codec that supports Full Rate and G.Lite asymmetric digital subscriber line (ADSL) transmission is described. The transmit channel consists of application-dependent digital filters, a 14-bit, 8.832-MSample/s current steering DAC, a 1.104-MHz analog filter, and a programmable attenuator. Due to extensive on-chip digital signal processing, the codec complies with the ADSL transmit power spectral density standards without external filtering. The receive channel contains -17.5 to 33.5 dB of programmable gain staggered strategically across three stages, a 138-kHz analog low-pass filter, a 14-bit, 2.208-MSample/s pipeline ADC, and a digital 138-kHz low-pass filter. The receive channel has a wide input range that can accommodate large line voltages present at the line hybrid circuit. The IC occupies 55.2 mm/sup 2/ and dissipates 450 mW from a 3.3-V supply.