학술논문
Performance and reliability of a 65nm Flash based FPGA
Document Type
Conference
Author
Source
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on. :1-3 Oct, 2012
Subject
Language
Abstract
We present a highly reliable Flash based FPGA fabricated with a 65nm embedded process. A very robust ON and OFF Vt window, over 8V, has been achieved with tight cell to cell distributions. 1k program/erase cycles have been performed and charge trap induced Vt window loss is less than 0.2V. Some initial Vt shift is seen at erase side after retention bake. The shift saturates after 24 hours and the post-bake Vt window is close to 8V. There is still a 2V margin from our design spec which is 6V. Operation disturb life time was extrapolated from an accelerated test. AC life time is greater than 2000 years. For some high security applications we provide a user-verify feature. Based on accelerated testing we have proposed the number of user verifies and predicted the error rate.