학술논문
A Novel Chiplet Integration Architecture Employing Pillar-Suspended Bridge with Polymer Fine-Via Interconnect
Document Type
Conference
Author
Source
2023 IEEE 73rd Electronic Components and Technology Conference (ECTC) ECTC Electronic Components and Technology Conference (ECTC), 2023 IEEE 73rd. :34-39 May, 2023
Subject
Language
ISSN
2377-5726
Abstract
We proposed a novel chiplet integration technology based on a new bridge architecture, which we call “Pillar-Suspended Bridge (PSB)”, for a wide range of applications including High-Performance Computing (HPC), those that require huge computing power for AI/Metaverse, mobile, and automotive. The technology enables one to connect directly between chiplets/bridges with simplest scheme and does not require a high-cost interposer and realizes “Integrated Circuit of the Integrated Circuits (MetaIC)”. In this paper, we describe the concept and experimental results of the manufacturing of PSB architecture and investigate the key technology to employing high-performance bridge with polymer RDL and dry-etched fine vias.