부산대학교 도서관

This paper describes a high-level multi-HDL design process applied to an industrial design of a single chip Videophone Codec. It makes use of many state-of-the-art design tools and methods: Behavioural VHDL control path synthesis for the controller of the Codec motion estimator; behavioural DSP synthesis from Silage to generate an application-specific calculation unit that performs vector prediction for the motion estimator; retargetable C compilation for an embedded application-specific microcontroller and multi-level (behavioural, RTL, gate) and multi-language (VHDL, Silage, C) co-simulation. We show that, with respect to a manual design process, the use of these tools led to the following results: a five-fold reduction in the source HDL description complexity; equal or better timing performance; silicon area within 15% (4% area overhead for the DSP operator, and 14% overhead for the controller) and automatically compiled assembly code (from ANSI C descriptions) that is as compact as hand-coded assembler. We also identified a strong need to pay attention to design verification issues, especially when dealing with multi-level descriptions and multiple languages. Validation of the design was the single most time consuming part of the process.