학술논문

On-Chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers
Document Type
Periodical
Source
IEEE Photonics Technology Letters IEEE Photon. Technol. Lett. Photonics Technology Letters, IEEE. 30(1):31-34 Jan, 2018
Subject
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Delays
Optical buffering
Optical waveguides
Delay lines
Adaptive optics
System-on-chip
Integrated optics
photonic integrated circuits
silicon photonics
integrated delay lines
time-slot interchanger
Language
ISSN
1041-1135
1941-0174
Abstract
We demonstrate integrated silicon-on-insulator (SOI) spiral waveguides with record-high 2.6-ns/mm 2 on-chip delay efficiency performing as delay bank stage in variable optical delay buffering and time-slot interchanger applications with 10-Gb/s optical packets. The micro-scale SOI chip comprises three integrated waveguide delay elements of different lengths, providing variable delays of 6.5, 11.3, and 17.2 ns, respectively. Utilizing two semiconductor optical amplifier Mach-Zehnder interferometer wavelength converters and on-chip packet delay, error-free on-chip variable delay buffering from 6.5 to 17.2 ns and successful time-slot interchanging for 10-Gb/s optical packets are presented.