학술논문
An area efficient 10-bit time mode hybrid DAC with current settling error compensation
Document Type
Conference
Source
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on. :1-4 Aug, 2015
Subject
Language
ISSN
1548-3746
1558-3899
1558-3899
Abstract
This work describes an area efficient 10-bit time mode hybrid DAC with current settling error compensation. The proposed 10-bit hybrid DAC is realized using a current steering DAC for the lower bits conversion and a time mode DAC for the upper bits conversion. The time mode DAC consist of a single capacitor, amplifier, current mirror and several control switches which occupies less area than other DAC architectures. In addition, the time mode DAC error due to improper current settling is suppressed by the pulse width compensation scheme which does not critically increase the area. The proposed DAC is realized using 0.35µm CMOS technology with estimated core area of 0.00463mm 2 , which is less than most of the existing 10-bit DACs. The maximum DNL and INL with error compensation showed 0.5LSB and −0.6LSB, respectively.