학술논문

Challenges in Low Power VLSI Design: A Review
Document Type
Conference
Source
2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA) Electronics, Communication and Aerospace Technology (ICECA), 2021 5th International Conference on. :191-195 Dec, 2021
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Robotics and Control Systems
Logic gates
Very large scale integration
FinFETs
Minimization
Delays
Power dissipation
Transistors
Threshold voltage
Subthreshold Conduction
Leakage Control Transistor (LCT)
power delay product
Language
Abstract
The need for decreasing the standby power in battery aided devices is the main design objective for very large-scale integration (VLSI) engineers. Many leakage controlling techniques have been designed so far each with its pros and cons. The focus of this paper is on the comparative study of the current best domino logic methods using FinFETs. The unity noise gain for SCDNDTDL is 3.77X higher than the SG FinFET logic. This paper will help the researchers to get a technical hunch of choosing a technique over another.