학술논문

3D Stacking of Heterogeneous Chiplets on Modified FOWLP Platform with Thru-Silicon Redistribution Layer
Document Type
Conference
Source
2023 IEEE 73rd Electronic Components and Technology Conference (ECTC) ECTC Electronic Components and Technology Conference (ECTC), 2023 IEEE 73rd. :24-28 May, 2023
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Photonics and Electrooptics
Radio frequency
Semiconductor device measurement
Three-dimensional displays
Stacking
Semiconductor device reliability
Electronic components
Inspection
3D stacking of chiplets
thru-Si RDL process integration
chip-to-wafer bonding
via chain measurement and reliability assessment
Language
ISSN
2377-5726
Abstract
A 3D stacking of CMOS on RF device chiplet is demonstrated for significant reduction of areal form factor for Front-End Module (FEM) application. The salient points of the process integration of thru-silicon redistribution layer on the backside of RF device wafer, chip-to-wafer bonding and assembly, measurement of the interconnection and reliability assessment will be discussed.