학술논문
A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer
Document Type
Conference
Author
Source
IEEE Custom Integrated Circuits Conference 2010 Custom Integrated Circuits Conference (CICC), 2010 IEEE. :1-4 Sep, 2010
Subject
Language
ISSN
0886-5930
2152-3630
2152-3630
Abstract
A wideband ΔΣ ADC using a novel double-sampling scheme with a single set of capacitors and a dynamic embedded-adder quantizer is presented. The proposed quantizer eliminates static currents in the adder of a low-distortion architecture. Fabricated in 0.18 µm CMOS process, the prototype chip operates with a 320 MHz sampling frequency and achieves 63 dB SNDR in a 20 MHz signal band while consuming 16 mW power.