학술논문

Impact of High Temperature Up to 175 °C on the DC and RF Performances of 22-nm FD-SOI MOSFETs
Document Type
Periodical
Source
IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 70(10):4987-4992 Oct, 2023
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Temperature measurement
Radio frequency
Logic gates
Temperature distribution
Capacitance
MOSFET
Performance evaluation
Figures of merit (FoMs)
fmax
fT
fully depleted silicon-on-insulator (FD-SOI)
high temperature
zero-temperature coefficient (ZTC) point
Language
ISSN
0018-9383
1557-9646
Abstract
In this work, the effect of rise in temperature from 25 °C to 175 °C on the performance of 22-nm fully depleted silicon-on-insulator (FD-SOI) MOSFETs is studied under different bias conditions. The devices are measured in dc and RF to observe the zero-temperature coefficient (ZTC) point and extract the prominent RF figures of merit (FoMs), i.e., current-gain cutoff frequency ( ${f} _{T}$ ) and maximum oscillation frequency ( ${f} _{\text {max}}$ ). The evolution of transconductance ( ${g} _{m}$ ) with temperature appears to be one of the major causes of the 20% degradation in peak ${f} _{T}$ and ${f} _{\text {max}}$ at 175 °C. From a low-power application point of view, stepping down ${V} _{d}$ from 0.8 to 0.6 V decreases the magnitude of peak ${f} _{T}$ and ${f} _{\text {max}}$ degradation to around 7%–10%, respectively, over the given temperature range while reducing static power consumption ( ${P} _{\text {dc}}$ ) around 29%. Furthermore, the variation of ${f} _{T}$ and ${f} _{\text {max}}$ at and below the ${g} _{m}$ -ZTC is investigated. Below the ${g} _{m}$ -ZTC point, at a front-gate bias ${V} _{g}$ of 0.3 V, an improvement in ${f} _{T}$ of around 20% and an almost steady ${f} _{\text {max}}$ are observed.