학술논문
Enhanced Reliability of 7nm Process Technology featuring EUV
Document Type
Conference
Author
Source
2019 Symposium on VLSI Technology VLSI Technology, 2019 Symposium on. :T16-T17 Jun, 2019
Subject
Language
ISSN
2158-9682
Abstract
In this paper, we report the reliability characterization of 7nm FinFET technology, in which the highly scaled 6 th generation of FinFETs and 256Mbit SRAM cells was newly developed by utilizing EUV. The single EUV patterning of MOL and BEOL resulted in significantly improved reliability distribution as compared to the previous nodes with multiple patterning techniques. The successful demonstration on product reliability including SRAM, Logic HTOL, and SER as technology evaluation was performed, indicating the 7nm technology+EUV is ready for high volume manufacturing.