학술논문
E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology
Document Type
Conference
Author
Shamanna, M.; Abuayob, E.; Aenuganti, G.; Alvares, C.; Antony, J.; Bahudhanam, A.; Chandran, A.; Chew, P.; Chatterjee, A.; Chauhan, B.; Dandeti, N.; Desai, J.; Doyle, M.; Dmukauskas, T.; Farache, P.; Fetzer, E.; Fischer, K.; Hack, P.; Greenzweig, Y.; Giacobbe, J.; Hafez, W.; Haralson, E.; Hegde, A.; Illa, A.; Islam, M.; Jain, S.; Jang, M.; Nguyen, J.; Tong, T.; Jiang, L.; Karl, E.; Kalangi, P.; Khoo, G.; Krishnamoorthy, A.; Kuns, B.; Li, W.; Livengood, R.; Malik, T.; Priyanka, R.; Faraby, H.; Maymon, Y.; Mistry, K.; Morgan, K.; Natarajan, S.; Nevo, O.; Oh, M.; Pardy, P.; Park, J.; Penmatsa, P.; Phelps, B.; Peterson, C.; Rajappa, S.; Raveh, A.; Rezaie, A; Ravishankar, T.; Ramaswamy, R.; Reddy, S.; Saha, R.; Sen, S.; Sanchez, R.; Sanaga, R.; Simkhovich, B.; Sell, B.; Senger, M.; Schnarch, B.; Seshadri, M.; Sidorov, O.; Subramaniam, S.; Subramanian, K.; Truong, B.; Bangalore, S.; Hicks, J.; Venkatesh, S.; Christensen, D.; Bhargav, K.; Haartman, M. Von; Joshi, P.; Zickel, S.; Lin, C-H; Huening, J.; Wu, T-H; Bakken, N.; Afzal, A.; Raman, A.; Rao, Sj.; Kawar, V.; Neirynck, J.; Bradley, D.; Duwe, M.; Wu, S.; Patil, V.; Bayoumy, M.
Source
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
Subject
Language
ISSN
2158-9682
Abstract
PowerVia Technology [1] is a novel innovation to extend Moore’s Law scaling by having Power Delivery on the backside. This paper presents the pre & post-silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of >90% in large areas of the core while showing >5% Frequency benefit in Silicon due to reduced IR drop. Successful Post-Silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristic of the PowerVia test-chip is in line with higher power densities expected from logic scaling.