학술논문
System Design Technology Co-Optimization for 3D Integration at
Document Type
Conference
Author
Song, S.C.; Nallapati, Giri; Khan, Irfan; Nikfar, Nader; Yan, Bohan; Miranda, Miguel; Lim, Bruce; Nagarajan, Mali; Park, Joon-Young; Srinivas, Vaishnav; Langari, Reza; Chava, Bharani; Sanaka, Venu; Boynapalli, Venu; Gupta, Paras; Pandey, Shree; Xie, Biancun; Feng, Peijie; Choi, Jihong; Rakshit, Titash; Shenoy, Ravi; Nemani, Mahadev; Verrilli, Colin; Zhu, John; Chen, Jun; Nakamoto, Mark; Zhao, Lily; Sun, Yangyang; Atallah, Francois; Kim, Jonghae; Attar, Rashid; Chidambaram, Chidi
Source
2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :22.3.1-22.3.4 Dec, 2021
Subject
Language
ISSN
2156-017X
Abstract
Partition of monolithic 2D (M2D) chip and heterogeneous integration of resultant chiplets are inevitable in the near future due to rising cost of transistor and complexity of process. 3D stacking is required to maintain tight cross-IP communication and fit into the limited footprint over Printed Circuit Board (PCB). We discuss criteria of choice for the 3DIC technology flavor and logic chiplet scaling knobs in terms of optimized key performance indicators (KPI) at system level.