부산대학교 도서관

Modern heterogeneous SoCs feature a mix of many hardware accelerators and general-purpose cores that run many applications in parallel. This brings challenges in managing how the accelerators access shared resources, e.g., the memory hierarchy, communication channels, and on-chip power. We address these challenges through flexible orchestration of data on a 74Tbps network-on-chip (NoC) for dynamic management of the resources under contention and a distributed hardware power management (DHPM) scheme. Developing and testing these ideas requires a comprehensive evaluation platform. Hence, we built an SoC that features 14 types of accelerators next to 4 RISC-V cores capable of running many simultaneous applications on top of a Linux-SMP operating system. Building such a platform was made possible in part by the reuse of open-source hardware (OSH) components [1]. However, even with a growing OSH community, the lack of available SoC designs keeps other researchers from performing evaluations of this kind; this is demonstrated by the unprecedented degree of heterogeneity and complexity of our chip compared to prior academic SoCs in the literature. To allow other academic and industrial research teams to pursue SoC design innovations without having to reinvent the wheel, we plan to publicly release the synthesizable design of our SoC with its software stack.