부산대학교 도서관

This paper presents a power and area efficient digital communication interface for tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible neural implant in a bus-like structure in order to realize a NeuroBus. The digital interface only requires 3 pins, does not need any preprogramming or trimming for address allocation and achieves a very low core area. The digital interface was implemented in a 1.2V 180nm CMOS technology and supports up to 100 spatially distributed neural recorder ASICs, consuming only $9\ \mu\mathrm{W}$ of power per channel on a tiny area of $2380\ \mu\mathrm{m}^{2}$.