학술논문
Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors
Document Type
Conference
Author
Source
2006 IEEE international SOI Conferencee Proceedings International SOI Conference, 2006 IEEE. :19-20 Oct, 2006
Subject
Language
ISSN
1078-621X
Abstract
We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations.