학술논문

Moving Down the Stack: Performance Evaluation of Packet Processing Technologies for Stateful Firewalls
Document Type
Conference
Source
NOMS 2023-2023 IEEE/IFIP Network Operations and Management Symposium Network Operations and Management Symposium, NOMS 2023-2023 IEEE/IFIP. :1-7 May, 2023
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineering Profession
Performance evaluation
Firewalls (computing)
Multithreading
Switches
Traffic control
Network security
Throughput
Language
ISSN
2374-9709
Abstract
Software-based network security solutions using SDN/NFV provide high flexibility and short development cycles, but may impose a bottleneck onto the network due to their lack of ASIC-based hardware packet processing. To overcome this limitation, several frameworks have emerged to enable flexible high speed packet processing in software, e.g., NAPI, XDP, or DPDK, or on programmable data planes in hardware, e.g., P4. Despite aiming for a common goal, the design principles of these technologies diverge, which raises the question of their suitability for critical security-related network functions, such as firewalls. In this work, we implement a stateful firewall, which is capable of tracking TCP state and sequence numbers, for each of the four aforementioned high speed packet processing technologies and make the firewall modules publicly available. We integrate multithreading strategies, where applicable, and discuss the impact of each packet processing technology during the development process. Finally, we evaluate and compare their performance in terms of throughput in two scenarios following the guidelines of RFC3511 in a 100 Gbps testbed.