부산대학교 도서관

Big Data, Artificial Intelligence (AI) and other scientific applications use multi-core systems to process data for disease and drug discovery, weather forecast, design automation, etc. However, multi-core systems are not always effective because not all applications are amenable to them, leading to the need for special-purpose architectures, e.g., accelerators. Also, large monolithic multi-core chips are more prone to manufacturing defects that dramatically reduce the wafer yield and increase the cost. The need for specialisation coupled with skyrocketing manufacturing costs led to the introduction of multi-chiplet systems. They integrate a set of heterogenous chiplets within a single package, where each chiplet is a smaller multi-core chip. In addition to on-chip communication within chiplets, now there is a need for an on-package communication infrastructure to facilitate data sharing among chiplets. Copper wire-based Network-on-Chip (NoC) and silicon interposer-based Network-on-Package (NoP) are the preferred infrastructures for on-chip and on-package communications. However, increasing core count within chiplets and diverse communication demands by different chiplets have exposed the limitations of NoC and NoP. Experts reported communication and not computation as the main bottleneck in emerging computing systems. This generated renewed interest in the exploration of NoC and NoP. The first goal of this panel is to discuss recent challenges in NoC and NoP with respect to performance, security and scalability. Then the panellists discuss exciting opportunities presented by the rise of new interconnect technologies, including 3D, optical and wireless; integration technologies, including, silicon interposer and multi-chip module; and computing paradigms, including in-memory, DNA and quantum. The final and most important goal is to engage panellists and attendees in a discussion about recent breakthroughs and innovations, and how the field could be moved forward.