학술논문
A graph based processor model for retargetable code generation
Document Type
Conference
Author
Source
Proceedings ED&TC European Design and Test Conference European design and test conference European Design and Test Conference, 1996. ED&TC 96. Proceedings. :102-107 1996
Subject
Language
ISSN
1066-1409
Abstract
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity the parallelism and all architectural peculiarities of an embedded processor In this paper; the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.