학술논문
A portable redundancy algorithm for capacitive/resistive SAR A/D converters
Document Type
Conference
Source
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS) Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on. :141-144 Dec, 2013
Subject
Language
Abstract
An algorithm, which can be used to add redundancy to existing SAR A/D converters for improving their performance, is presented. It needs very small extra analog area and preserves the intrinsic immunity to metastability of a classical SAR algorithm. A 14b Successive Approximation Register (SAR) A/D Converter, equipped with this algorithm, has been designed in a 40nm CMOS process to be embedded in a System-on-Chip (SoC). Maximum DNL/INL of 1.4LSB/3.0LSB and an Effective Number of Bits (ENOB) of 12.0 have been measured.