학술논문

A Four-Element 500-MHz 40-mW 6-bit ADC-Enabled Time-Domain Spatial Signal Processor
Document Type
Periodical
Source
IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 56(6):1784-1794 Jun, 2021
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Array signal processing
Interference
Phased arrays
Time-domain analysis
Transmitters
Frequency modulation
Delays
Kronecker decomposition
spatial signal processor (SSP)
time-domain processing
true-time delay
Language
ISSN
0018-9200
1558-173X
Abstract
Next-generation wireless communication requires phased-array systems with large modulated bandwidths and high energy efficiency, ensuring Gb/s data communication. Conventional phase-shifter-based arrays result in frequency-dependent processing and, therefore, beam-squinting in an array. This work demonstrates a four-element 500-MHz modulated bandwidth true-time-delay-based ADC-enabled spatial signal processor (SSP) with frequency-uniform beamforming, wideband beam-nulling, and multiple independent interference filterings using the Kronecker decomposition. This processor can augment conventional phased-array RF front ends to implement a complete antenna-to-digital solution. The proposed baseband delay-compensating solution in the SSP uses scalable time-domain circuits comprising of time-interleaved voltage-to-time converters followed by asynchronous 6-bit pipeline time-to-digital converters and consumes only 40 mW with a total area of 0.31 mm 2 in 65-nm CMOS technology.