학술논문
14-bit, 2.2MS/s sigma delta ADCs
Document Type
Conference
Author
Source
Proceedings of the 25th European Solid-State Circuits Conference Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European. :82-85 1999
Subject
Language
Abstract
This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a .35µM CMOS, double poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation.