학술논문
A Parallel PLA Minimization Program
Document Type
Conference
Author
Source
24th ACM/IEEE Design Automation Conference Design Automation, 1987. 24th Conference on. :600-607 1987
Subject
Language
ISSN
0738-100X
Abstract
In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.