학술논문

Circuit and platform design challenges in technologies beyond 90nm
Document Type
Conference
Source
2003 Design, Automation and Test in Europe Conference and Exhibition Design, automation and test in Europe Design, Automation and Test in Europe Conference and Exhibition, 2003. :44-47 2003
Subject
Computing and Processing
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Circuits
Moore's Law
Transistors
Costs
Silicon
Geometry
Design optimization
Design methodology
Terminology
History
Language
ISSN
1530-1591
Abstract
There are already a huge number of problems for silicon designers and it is likely to just get worse. Many of these problems are technical, associated with shrinking geometries and increasing architecture complexities, but there are a significant number that seem to be caused by procedurally related mistakes and issues. Many of the technical problems are solved and re-solved on a piecemeal basis, focusing on local optimizations of small design-space problems. Unfortunately, many of these local solutions really create a less apparent but larger inefficiency in the whole design flow. The reason for this is that few ever look at the whole design methodology, especially as it applies to large design teams. As a consequence, this lack of oversight for the whole methodology is causing project procedural problems and inefficiencies.