학술논문
Simulation, synthesis, and verification of pipelined asynchronous VLSI circuits
Document Type
Conference
Author
Source
TENCON '97 Brisbane - Australia. Proceedings of IEEE TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications (Cat. No.97CH36162) TENCON '97 TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications., Proceedings of IEEE. 2:445-448 vol.2 1997
Subject
Language
Abstract
Systolic arrays are a powerful implementation method for signal, image and video processing algorithms which operate on continuous data streams. While systolic arrays assume a synchronous clocking scheme, similar regular pipelined processing networks can be based on an asynchronous timing model, with resulting advantages in terms of modularity, speed, and power consumption. Unfortunately there is little expertise or CAD support for the system level design of asynchronous pipelined data networks. This paper presents a modelling methodology for these networks based on functions operating on lists of data values, allowing computations to be described in terms of the sequence of data values processed without explicitly assigning times to the individual operations. It describes strategies and accompanying CAD tools for using this methodology for system specification, simulation, verification, and synthesis.