부산대학교 도서관

In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.