학술논문

POSTER: A Memory-Access-Efficient Adaptive Implementation of kNN on FPGA through HLS
Document Type
Conference
Source
2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT) Parallel Architectures and Compilation Techniques (PACT), 2019 28th International Conference on. :503-504 Sep, 2019
Subject
Computing and Processing
Field programmable gate arrays
Kernel
Servers
Graphics processing units
Bandwidth
Feature extraction
Databases
kNN
FPGA
High-level synthesis
principal component analysis
Low-precision data representation
Memory-accessefficient
Language
ISSN
2641-7936
Abstract
Implementing an efficient k-Nearest Neighbors(kNN) algorithm on FPGA is becoming challenging due to the fact that both the size and dimensionality of datasets that kNN is working on have been rapidly growing, which may incur a performance bottleneck on the memory-access. To reduce the impact of the memory-access constraint, in this paper we implement two kNN kernels through high-level synthesis (HLS) on FPGA by employing two data access reduction methods: low-precision data representation and principal component analysis based filtering (PCAF). One kernel is called MBFSkNN (Memory-efficient Brute-Force Searching kNN) and the other is called MPCAF-kNN (Memory-efficient PCAF kNN). Both kernels have been highly optimized to fully exploit the characteristics of FPGA. Besides, they are adaptive to the number of dimensions (D), number of data points in a database (N), number of nearest neighbors (k), number of bits per feature (B), and number of principal components (d). We evaluate the two kernels by comparing them with two state-of-the-art kNN implementations on a high-end CPU server, an existing BFS-kNN kernel on FPGA, and an existing BFS-kNN kernel on GPU. Our results show that the external memory accesses of these two kernels are greatly reduced and our design outperforms the existing ones.