학술논문
A heterogeneous SDR MPSoC in 28nmCMOS for low-latency wireless applications
Document Type
Conference
Author
Haas, Sebastian; Seifert, Tobias; Nothen, Benedikt; Scholze, Stefan; Hoppner, Sebastian; Dixius, Andreas; Adeva, Esther Perez; Augustin, Thomas; Pauls, Friedrich; Moriam, Sadia; Hasler, Mattis; Fischer, Erik; Yong Chen; Matus, Emil; Ellguth, Georg; Hartmann, Stephan; Schiefer, Stefan; Cederstrom, Love; Walter, Dennis; Henker, Stephan; Hanzsche, Stefan; Uhlig, Johannes; Eisenreich, Holger; Weithoffer, Stefan; Wehn, Norbert; Schuffny, Rene; Mayr, Christian; Fettweis, Gerhard
Source
2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE. :1-6 Jun, 2017
Subject
Language
Abstract
Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 × 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 µs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.