학술논문
Superior metal step coverage and dielectric quality in a simple two-level metal 1.0 mu m CMOS technology
Document Type
Conference
Source
Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE. :55-61 1989
Subject
Language
Abstract
A two-level metal process for a fourth-generation 1.0- mu m CMOS technology has been developed which yields superior aluminum step coverages and high-quality dielectrics without introducing complicated processing sequences. The process is cost-effective since it includes traditional materials and high throughput operations and is readily extendable to three levels of metal. The process incorporates a highly smoothed BPSG for dielectric I and resist-etchback planarization of plasma-enhanced TEOS for dielectric II. Also featured are a tapered aluminum I profile and modified contact window and via etch profiles. Defect density and electromigration data predict excellent yield and reliability for this process.ETX