부산대학교 도서관

RISC-V (pronounced "risk-five") is an open, free Instruction Set Architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Many implementations have been developed lately, each using different micro microarchitecture to support a set of standard as well as user-defined extensions. In order to meet this evolution, emerges the need for a fast, reusable and implementation independent test bases for the early verification of these cores. In this paper, we present a reusable framework for the end to end verification of RISC-V cores against the ISA specs using the Universal Verification Methodology (UVM). The proposed UVM environment is highly portable and reconfigurable as well to fit various architectures with minor modifications. We have implemented a predictor model using a modifiable and implementation-free approach that facilitates the easy addition of user-defined extensions. The environment also uses sequence layering to apply a wide range of complex scenarios and test cases.