부산대학교 도서관

With increasing digital systems complexity introduced by the sophisticated architectures, design verification becomes challenging and crucial. Verification is required to provide enough confidence in the design before proceeding with further expensive design stages, thus reliable reference models are needed. Developing an efficient reference model is not an easy task and may cause delays in the verification process increasing the time-to-market. This work elaborates the advantages of using high-level language reference models over the conventional SystemVerilog ones in digital design verification. Comparison between Python, C/C++, SystemC, Matlab, and conventional SystemVerilog reference models is explained from the perspectives of the run-time, memory consumption, complexity of implementation and UVM-reference model interface. A separate Universal Verification Methodology (UVM) environment is implemented for each reference model.