학술논문
Energy Efficiency Boost in the AI-Infused POWER10 Processor
Document Type
Conference
Author
Thompto, Brian W.; Nguyen, Dung Q.; Moreira, Jose E.; Bertran, Ramon; Jacobson, Hans; Eickemeyer, Richard J.; Rao, Rahul M.; Goulet, Michael; Byers, Marcy; Gonzalez, Christopher J.; Swaminathan, Karthik; Dhanwada, Nagu R.; Muller, Silvia M.; Wagner, Andreas; Sadasivam, Satish Kumar; Montoye, Robert K.; Starke, William J.; Zoellin, Christian G.; Floyd, Michael S.; Stuecheli, Jeffrey; Chandramoorthy, Nandhini; Wellman, John-David; Buyuktosunoglu, Alper; Pflanz, Matthias; Sinharoy, Balaram; Bose, Pradip
Source
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) ISCA Computer Architecture (ISCA), 2021 ACM/IEEE 48th Annual International Symposium on. :29-42 Jun, 2021
Subject
Language
ISSN
2575-713X
Abstract
We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at socket level. In addition, a new feature supporting inline AI acceleration was added to the POWER ISA and incorporated into the POWER10 processor core design. The resulting boost in SIMD/AI socket performance is projected to be up to 10x for FP32 and 21x for INT8 models of ResNet-50 and BERT-Large. In this paper, we describe the novel methodology deployed and used not only to obtain these efficiency boosts for traditional workloads, but also to infuse AI/ML/HPC capability directly into the POWER10 core.