학술논문

On hazard-free patterns for fine-delay fault testing
Document Type
Conference
Source
2004 International Conferce on Test International test conference Test Conference, 2004. Proceedings. ITC 2004. International. :213-222 2004
Subject
Components, Circuits, Devices and Systems
Signal Processing and Analysis
Power, Energy and Industry Applications
Circuit faults
Fault detection
Logic testing
Automatic test pattern generation
Circuit testing
Test pattern generators
Hazards
Delay effects
Filters
Manufacturing
Language
Abstract
This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens. The method is based on grouping conventional delay-fault patterns into sets of almost equal-length paths. This narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults. These small delay faults are otherwise undetectable because they are masked by longer paths. A requirement for this method is to have hazard-free paths. To obtain these (almost) hazard-free paths we use a fast and simple postprocessing step that filters out paths with hazards. The experimental data shows the effectiveness and the necessity of this filtering process.