학술논문

Yield optimization in the mature fab
Document Type
Conference
Source
2001 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (IEEE Cat. No.01CH37160) Advanced semiconductor manufacturing Advanced Semiconductor Manufacturing Conference, 2001 IEEE/SEMI. :193-200 2001
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Probes
Investments
Data systems
Fabrication
Manufacturing automation
Cost function
Demography
Productivity
Robustness
Testing
Language
ISSN
1078-8743
Abstract
This paper provides the authors' insights and discussions in four areas of yield optimization available to the mature semiconductor fabricator. The mature fab is arbitrarily defined as fabs older than 3 years having feature sizes of >0.5 /spl mu/m. The areas of yield optimization include: (1) cost and implementation considerations for an integrated data collection and information analysis system; (2) use of a quantified and partitioned D/sub 0/ yield model; (3) focus on baseline yield quantification and improvement practices versus excursion controls; (4) increased roles and responsibilities for yield improvement.