부산대학교 도서관

This article presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8 GS/s intermediate frequency (IF) sampling for a 1 GHz bandwidth input spanning from 1.5 GHz to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove the distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130 nm BiCMOS technology using SiGe heterojunction bipolar transistors (HBTs) to buffer and sample the wide-band input. Potential inclusion of this BiCMOS SHA in a subsequent high-speed ADC design provides the possibility for a monolithic high performance converter solution. This independent sampling front-end occupies a core chip area of 0.6 mm 2 . The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers (THA), a high-speed clock driver, and externally adjustable current mirror biases. Measurements of the fabricated SHA show a 10-bit effective resolution across the 1 GHz bandwidth and > 61 dBc spurious free dynamic range (SFDR).