부산대학교 도서관

A power- and area-efficient Low Voltage Differential Signaling (LVDS) AC coupled receiver for short links is presented. The receiver accommodates the wide LVDS common-mode range without requiring large, board-mounted AC coupling capacitors or a slow, rail-to-rail input stage. Instead, a small, on-chip coupling capacitance generates a pseudo return-to-zero (RZ) pulse that is latched into the receiver via output feedback to bias switches. This reduces the effects of baseline wander caused by DC imbalanced data streams without the need for encoding or scrambling, while outputting a full-scale CMOS digital signal. The receiver is implemented in a 130 nm SiGe BiCMOS (f T = 200 GHz) technology and is tested with a 100 mV p-p differential PRBS15, demonstrating a BER of < 10 −12 . The design includes low and high power modes characterized at 8 Gb/s consuming 3.7 mW and at 10 Gb/s consuming 5.1 mW, respectively. A peak efficiency of 0.46 mW/Gb/s is recorded in the low power mode. The design occupies 0.0115 mm 2 , including the on-chip coupling capacitance.