학술논문

CMOS Gate Oxide Integrity Failure Structure Analysis Using Transmission Electron Microscopy
Document Type
Conference
Source
2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on. :2190-2192 2006
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Failure analysis
Transmission electron microscopy
Electric breakdown
Cobalt
Fault location
Optical beams
Semiconductor device manufacture
Semiconductor devices
Circuit faults
Silicon
Language
Abstract
In this paper, cross-sectional TEM combined with plan-view TEM analysis was employed to investigate the gate oxide integrity (GOI) failure isolated using infrared optical beam induced resistance change (IR-OBIRCH) method. The cross-sectional TEM investigation only shows gate oxide breakdown and fused active under the spacer. However, plan-view TEM analysis reveals clearly the breakdown happened at the poly edge due to smaller spacer related to over etch of spacer nitride or oxide. EF-TEM elemental mapping shows Co migrates electrically to the fused active area