학술논문
Survey of design and process failure modes for high-speed SerDes in nanometer CMOS
Document Type
Conference
Author
Source
23rd IEEE VLSI Test Symposium (VTS'05) VLSI test symposium VLSI Test Symposium, 2005. Proceedings. 23rd IEEE. :285-291 2005
Subject
Language
ISSN
1093-0167
2375-1053
2375-1053
Abstract
This paper gives an overview of reported design-and process-related electrical performance failure modes for high-speed (> 1 GHz) serial interfaces fabricated using CMOS processes /spl les/130 nm. Effects of various defects on observable performance at the I/O pins are summarized, along with ATE test technology implications.