학술논문
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM
Document Type
Conference
Author
Takashima, Daisaburo; Shiga, Hidehiro; Hashimoto, Daisuke; Miyakawa, Tadashi; Shiratake, Shinichiro; Hoya, Katsuhiko; Ogiwara, Ryu; Takizawa, Ryosuke; Doumae, Sumiko; Fukuda, Ryo; Watanabe, Yohji; Fujii, Shuso; Ozaki, Tohru; Kanaya, Hiroyuki; Shuto, Susumu; Yamakawa, Koji; Kunishima, Iwao; Hamamoto, Takeshi; Nitayama, Akihiro
Source
2010 IEEE International Solid-State Circuits Conference - (ISSCC) Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International. :262-263 Feb, 2010
Subject
Language
ISSN
0193-6530
2376-8606
2376-8606
Abstract
A ferroelectric RAM, especially Chain FeRAM ™ [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write band-width by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.